Wafer Backside Structures Having Copper Pillars

ABSTRACT

An integrated circuit structure includes a semiconductor substrate having a front side and a backside, and a conductive via penetrating the semiconductor substrate. The conductive via includes a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is on the backside of the semiconductor substrate and electrically connected to the back end of the conductive via. A passivation layer is over the RDL, with an opening in the passivation layer, wherein a portion of the RDL is exposed through the opening. A copper pillar has a portion in the opening and electrically connected to the RDL.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of the following provisionally filed U.S. patent application: Application Ser. No. 61/174,339, filed Apr. 30, 2009, and entitled “Wafer Backside Structures Having Copper Pillars,” which application is hereby incorporated herein by reference.

This application is related to following commonly-assigned U.S. patent Applications: application Ser. No. 12/332,934, filed Dec. 11, 2008, and entitled “Backside Connection to TSVs Having Redistribution Lines,” and application Ser. No. 12/347,742, filed Dec. 31, 2008, and entitled “Bond Pad Connection to Redistribution Lines Having Tapered Profiles,” which applications are hereby incorporated herein by reference.

TECHNICAL FIELD

This invention relates generally to integrated circuit structures, and more particularly to through-silicon vias, and even more particularly to the formation of bond pads connected to the through-silicon vias.

BACKGROUND

Since the invention of integrated circuits, the semiconductor industry has experienced continuous rapid growth due to constant improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, allowing more components to be integrated into a given chip area.

These integration improvements are essentially two-dimensional (2D) in nature, in that the volume occupied by the integrated components is essentially on the surface of the semiconductor wafer. Although dramatic improvements in lithography have resulted in considerable improvements in 2D integrated circuit formation, there are physical limitations to the density that can be achieved in two dimensions. One of these limitations is the minimum size needed to make these components. Also, when more devices are put into one chip, more complex designs are required.

An additional limitation comes from the significant increase in the number and lengths of interconnections between devices as the number of devices increases. When the number and the lengths of interconnections increase, both circuit RC delay and power consumption increase.

Among the efforts for resolving the above-discussed limitations, three-dimensional integrated circuit (3DIC) and stacked dies are commonly used. Through-silicon vias (TSVs) are thus used in 3DIC and stacked dies. In this case, TSVs are often used to connect the integrated circuits on a die to the backside of the die. In addition, TSVs are also used to provide short grounding paths for grounding the integrated circuits through the backside of the die, which may be covered by a grounded metallic film.

FIG. 1 illustrates a conventional TSV 102 formed in chip 104. TSV 102 is in silicon substrate 106. Through the interconnections (metal lines and vias, not shown) in the metallization layers, TSV 102 is electrically connected to bond pad 108, which is on the front surface of chip 104. TSV 102 is exposed through the back surface of silicon substrate 106 in the form of a copper post. When chip 104 is bonded to another chip, TSV 102 is bonded to a bond pad on the other chip, with or without solder therebetween.

The conventional backside TSV connection suffers from drawbacks. Since the TSV bonding requires relatively large pitch between TSVs, the locations of the TSVs are restricted and the distance between the TSVs needs to be big enough to allow room for, for example, solder balls. New backside structures are thus needed.

SUMMARY OF THE INVENTION

In accordance with one aspect of the present invention, an integrated circuit structure includes a semiconductor substrate having a front side and a backside, and a conductive via penetrating the semiconductor substrate. The conductive via includes a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is on the backside of the semiconductor substrate and electrically connected to the back end of the conductive via. A passivation layer is over the RDL, with an opening in the passivation layer, wherein a portion of the RDL is exposed through the opening. A copper pillar has a portion in the opening and is electrically connected to the RDL.

Other embodiments are also disclosed.

The advantageous features of the present invention include improved bondability and increased standoff between stacked dies.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIG. 1 illustrates a conventional integrated circuit structure including a through-silicon via (TSV), wherein the TSV protrudes through the backside of a substrate, and is bonded to a bond pad on another chip in the form of a copper post;

FIGS. 2 through 11 are top views and cross-sectional views of intermediate stages in the manufacturing of an interconnect structure in accordance with an embodiment; and

FIGS. 12 and 13 are top views and cross-sectional views of intermediate stages in the manufacturing of an interconnect structure in accordance with another embodiment.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the embodiments of the present invention are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

A novel backside connection structure connecting to through-silicon vias (TSVs) and the method of forming the same are provided. The intermediate stages in the manufacturing of an embodiment of the present invention are illustrated. The variations of the embodiments are discussed. Throughout the various views and illustrative embodiments of the present invention, like reference numbers are used to designate like elements.

Referring to FIG. 2, chip 2, which includes substrate 10 and integrated circuits (symbolized by block 4) therein, is provided. In an embodiment, chip 2 is a portion of wafer including a plurality of chips identical to chip 2. Substrate 10 may be a semiconductor substrate, such as a bulk silicon substrate, although it may include other semiconductor materials such as group III, group IV, and/or group V elements. Semiconductor devices such as transistors (also illustrated by block 4) may be formed at the front surface (the surface facing up in FIG. 2) of substrate 10. Interconnect structure 12, which includes metal lines and vias (not shown) formed therein, is formed over substrate 10 and connected to the semiconductor devices. The metal lines and vias may be formed of copper or copper alloys, and may be formed using the well-known damascene processes. Interconnect structure 12 may include commonly known inter-layer dielectric (ILD) and inter-metal dielectrics (IMDs).

TSV 20 is formed in substrate 10, and extends from the back surface (the surface facing down in FIG. 2) to the front surface (the surface with active circuits formed thereon). In a first embodiment, as shown in FIG. 2, TSV 20 is formed using a via-first approach, and is formed before the formation of a bottom metallization layer (commonly known as M1). Accordingly, TSV 20 only extends into the ILD that is used to cover the active devices, but not into the IMD layers in interconnect structure 12. In alternative embodiments, TSV 20 is formed using a via-last approach, and is formed after the formation of interconnect structure 12. Accordingly, TSV 20 penetrates through both substrate 10 and interconnect structure 12. Isolation layer 22 is formed on the sidewalls of TSV 20, and electrically insulates TSV 20 from substrate 10. Isolation layer 22 may be formed of commonly used dielectric materials such as silicon nitride, silicon oxide (for example, tetra-ethyl-ortho-silicate (TEOS) oxide), and the like.

Referring to FIG. 3, bond pad 14 is formed on the front side (the side facing up in FIG. 3) of, and protrudes beyond, the front surface of chip 2. Chip 2 (and the corresponding wafer) is then mounted on carrier wafer 16 through glue 18. In FIG. 4, a backside grinding is performed to remove excess portion of substrate 10. A chemical mechanical polish (CMP) is performed to the backside of chip 2, so that TSV 20 is exposed. Backside isolation layer 24 is formed to cover the backside of substrate 10. In an exemplary embodiment, the formation of backside isolation layer 24 includes etching back the back surface of substrate 10, blanket forming backside isolation layer 24, and performing a light chemical mechanical polish (CMP) to remove the portion of backside isolation layer 24 directly over TSV 20. Accordingly, TSV 20 is exposed through an opening in backside isolation layer 24. In alternative embodiments, the opening in backside isolation layer 24, through which TSV 20 is exposed, is formed by etching.

Referring to FIG. 5, thin seed layer 26, also referred to as an under-bump metallurgy (UBM), is blanket formed on backside isolation layer 24 and TSV 20. The usable materials of UBM 26 include copper or copper alloys. However, other metals, such as silver, gold, aluminum, and combinations thereof, may also be included. In an embodiment, UBM 26 is formed using sputtering. In other embodiments, electro plating may be used.

FIG. 5 also illustrates the formation of mask 46. In an embodiment, mask 46 is a photoresist. Alternatively, mask 46 is formed of dry film, which may include an organic material such as Ajinimoto buildup film (ABF). Mask 46 is then patterned to form opening 50 in mask 46, with TSV 20 being exposed through opening 50.

In FIG. 6, opening 50 is selectively filled with a metallic material, forming redistribution line (RDL) 52 in opening 50. In the preferred embodiment, the filling material includes copper or copper alloys, although other metals, such as aluminum, silver, gold, or combinations thereof, may also be used. The formation methods may include electro-chemical plating (ECP), electroless plating, or other commonly used deposition methods such as sputtering, printing, and chemical vapor deposition (CVD) methods. Mask 46 is then removed. As a result, the portions of UBM 26 underlying mask 46 are exposed.

Referring to FIG. 7, the exposed portions of UBM 26 are removed by a flash etching. The remaining RDL 52 may include RDL strip (also referred to as a redistribution trace) 52 ₁ that includes a portion directly over, and connected to, TSV 20, and optionally RDL pad 52 ₂ joining RDL strip 52 ₁. A top view of RDL 52 may be found in FIG. 9. In FIG. 7 and subsequent figures, UBM 26 is not shown since it is typically formed of similar materials as RDL 52, and thus it appears to be merged with RDL 52. As a result of the flash etching, a thin layer of RDL 52 is also removed. However, the removed portion of RDL 52 is negligible compared to its overall thickness.

Next, as shown in FIG. 8, passivation layer 56 is blanket formed and patterned to form opening 58. Passivation layer 56 may be formed of nitrides, oxides, polyimide, and the like. Photo resist 60 is applied and developed to define the pattern of opening 58. A portion of RDL pad 52 ₂ is exposed through opening 58 in passivation layer 56. Opening 58 may occupy a center portion of RDL pad 52 ₂ (please refer to FIG. 9). RDL strip portion 52 ₁ may remain to be covered by passivation layer 56.

FIG. 9 illustrates a schematic top view of passivation opening 58 and RDL 52. Please note that the dimensions of the illustrated features are not in scale. Preferably, opening 58 has a size smaller than, and exposes a center portion of, RDL pad 52 ₂. In an exemplary embodiment, RDL strip 52 ₁ has a width W1 between about 5 μm and about 15 μm. RDL pad 52 ₂ has a width W2 of about 80 μm to about 100 μm, while passivation opening 58 has a width W3 of about 70 μm to about 90 μm. The top view of passivation opening 58 may have the shape of any polygon including, but not limited to, octagon, hexagon, square, or any other applicable shape.

Next, as shown in FIG. 10, photo resist 60 is removed, and photo resist 62 is formed. Photo resist 62 is preferably thicker than photo resist 60. In an embodiment, the thickness of photo resist 62 is greater than about 20 μm, or even greater than about 60 μm. Photo resist 62 is patterned to form an opening (also denoted as 58), through which RDL pad 52 ₂ is exposed. Next, copper pillar 64 is formed starting from opening 58 by electro plating. Copper pillar 64 may comprise copper and/or other metals such as silver, gold, tungsten, aluminum, and combinations thereof.

It is observed that in the etching of passivation layer 56 (FIG. 8), polymer may be generated, and the residue polymer in opening 58 may affect the formation of any nickel layer in opening 58. Further, any metal feature formed in opening 58 may be electrically connected to the circuit in chip 2. If electroless plating is used to form a metal feature in opening 58, there may be a possibility that the voltage potential of the circuit portions connected to the metal feature in opening 58 is affected. In embodiments of the present invention, however, electro plating is used in the formation of copper pillar 64 to solve these problems.

With the electro plating, copper pillar 64 may be reliably formed, and will have good quality. Also, the deposition rate of electro plating is high. Accordingly, copper pillar 64 may be deposited to a thickness significantly greater than the metal features deposited using electroless plating. In an exemplary embodiment, the height H of copper pillar 64 is greater than about 15 μm, or even greater than about 60 μm. Next, barrier layer 66 is formed, for example, by electroless plating, wherein barrier layer 66 may be formed of nickel. Alternatively, barrier layer 66 may comprise vanadium (V), chromium (Cr), and combinations thereof. Solder 68 may also be formed on top of barrier layer 66, and may also be formed using electro plating. In an embodiment, solder 68 includes a eutectic solder material formed of tin-lead (Sn—Pb) alloy. In alternative embodiments, solder 68 is formed of a lead-free solder material such as Sn—Ag or Sn—Ag—Cu alloy. It is noted that barrier layer 66 and solder 68 have sidewalls substantially aligned to the sidewalls of copper pillar 64. Further, barrier layer 66 and solder 68 are limited to the region directly over copper pillar 64.

Referring to FIG. 11, photo resist 62 is removed, and the structure as shown in FIG. 10 may be bonded to another chip such as chip 80. In an exemplary embodiment, chip 80 has copper post 86, barrier layer 84, and solder 82 on its front surface, wherein solders 82 and 68 may be reflowed to join each other.

FIGS. 12 and 13 illustrate an alternative embodiment. The initial steps of this embodiment may be essentially the same as illustrated in FIGS. 2 through 9. Next, referring to FIG. 12, after the formation of copper pillar 64 and without forming barrier layer 66, photo resist 62 is removed. Next, as shown in FIG. 13, metal finish 90 is formed. The formation methods of metal finish 90 include ECP, electroless plating, and the like. In an embodiment, metal finish 90 includes nickel layer 92 directly on, and contacting, copper pillar 64. Further, metal finish 90 covers the top of copper pillar 64 and is on sidewalls of copper pillar 64. Optionally, additional layers may be formed, so that metal finish may be an electroless nickel immersion gold (ENIG), a nickel electroless palladium immersion gold (ENEPIG), or a nick palladium layer. Metal finish 90 may also be joined to solder 82 in chip 80.

The embodiments of the present invention have several advantageous features. By forming copper pillar 64 using electro-plating instead of using electroless plating, the deposition rate is much higher, and hence the height of copper pillar 64 may reach tens of microns in a reasonably short time. The standoff between chips 2 and 80 (refer to FIGS. 11 and 13) may thus be increased, so that in the subsequent packaging process, underfill may easily flow into the space between chips 2 and 80.

Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the invention. 

1. An integrated circuit structure comprising: a semiconductor substrate comprising a front side and a backside; a conductive via penetrating the semiconductor substrate, the conductive via comprising a back end extending to the backside of the semiconductor substrate; a redistribution line (RDL) on the backside of the semiconductor substrate and electrically connected to the back end of the conductive via; a passivation layer over the RDL, with an opening in the passivation layer, wherein a portion of the RDL is exposed through the opening; and a copper pillar having a portion in the opening and electrically connected to the RDL.
 2. The integrated circuit structure of claim 1, wherein the RDL comprises: an RDL strip comprising a portion directly over, and contacting, the conductive via; and an RDL pad having a greater width than the RDL strip, wherein the copper pillar comprises a bottom surface contacting a top surface of the RDL pad.
 3. The integrated circuit structure of claim 1 further comprising: a barrier layer directly over the copper pillar; and a solder layer directly over the barrier layer, wherein sidewalls of the copper pillar, the barrier layer, and the solder layer are substantially vertically aligned.
 4. The integrated circuit structure of claim 1 further comprising a metal finish on a top surface and sidewalls of the copper pillar, wherein the metal finish comprises a metal selected from the group consisting essentially of nickel, gold, palladium, and combinations thereof.
 5. The integrated circuit structure of claim 1, wherein the copper pillar has a height greater than about 15 μm.
 6. The integrated circuit structure of claim 1, wherein the copper pillar comprises a top surface higher than a top surface of the passivation layer.
 7. The integrated circuit structure of claim 1, wherein the conductive via extends from the backside of the semiconductor substrate to the front side of the semiconductor substrate.
 8. An integrated circuit structure comprising: a semiconductor substrate comprising a front side and a backside; a conductive via extending from the backside of the semiconductor substrate into the semiconductor substrate, wherein a back end of the conductive via is exposed through the backside of the semiconductor substrate; a redistribution line (RDL) over the backside of the semiconductor substrate and connected to the back end of the conductive via, the RDL comprising: an RDL strip contacting the conductive via; and an RDL pad having a greater width than the RDL strip, wherein the RDL pad joins the RDL strip; a passivation layer over the RDL; an opening in the passivation layer, wherein a middle portion of the RDL pad is exposed through the opening, and wherein edge portions of the RDL pad are covered by the passivation layer; and a copper pillar in the opening and contacting the middle portion of the RDL.
 9. The integrated circuit structure of claim 8, wherein the copper pillar has a thickness greater than about 15 μm.
 10. The integrated circuit structure of claim 8 further comprising a nickel layer over and contacting the copper pillar.
 11. The integrated circuit structure of claim 10 further comprising a solder layer directly over the nickel layer, and wherein the solder layer and the nickel layer are substantially limited to a region directly over the copper pillar.
 12. The integrated circuit structure of claim 10, wherein the nickel layer comprises a portion directly over the copper pillar, and wherein the integrated circuit structure further comprises a gold layer over the nickel layer.
 13. The integrated circuit structure of claim 10, wherein the nickel layer comprises a portion directly over the copper pillar, and wherein the integrated circuit structure further comprising a palladium layer over the nickel layer.
 14. A method of forming an integrated circuit structure, the method comprising: providing a semiconductor substrate comprising a front side and a backside; providing a conductive via penetrating the semiconductor substrate, the conductive via comprising a back end extending to the backside of the semiconductor substrate; forming a redistribution line (RDL) on the backside of the semiconductor substrate and connected to the back end of the conductive via; forming a passivation layer over the RDL; forming an opening in the passivation layer, with a portion of the RDL being exposed through the opening; and forming a copper pillar having a portion in the opening, wherein the copper pillar is electrically connected to, and over, the RDL.
 15. The method of claim 14, wherein the step of forming the copper pillar comprises electro plating.
 16. The method of claim 15 further comprising: forming a photo resist over the passivation layer, wherein the photo resist is filled into the opening; before the step of forming the copper pillar, patterning the photo resist so that the opening in the passivation layer is exposed through the photo resist; after the step of forming the copper pillar, electro plating a barrier layer on the copper pillar; plating a solder layer on the barrier layer; and removing the photo resist after the step of plating the solder layer.
 17. The method of claim 15 further comprising: before the step of forming the copper pillar, forming a photo resist over the passivation layer, wherein the photo resist is filled into the opening; before the step of forming the copper pillar, patterning the photo resist so that the opening in the passivation layer is exposed through the photo resist: after the step of forming the copper pillar, removing the photo resist; after the step of removing the photo resist, forming a metal finish on a top surface and sidewalls of the copper pillar.
 18. The method of claim 14, wherein the copper pillar has a height greater than about 15 μm.
 19. The method of claim 14, wherein the RDL comprises copper. 